module top (
           input m_rst_n,       //主机复位
           input m_clk,        //主机时钟
           input m_ready,        //从机接收的数据已经准备就绪
           output m_valid,        //主机发送数据有效
           output [7: 0] m_data,

           input s_rst_n,       //从机复位
           input s_clk,       //从机时钟
           input s_valid,       //接收到有效数据
           output s_ready,      //准备好接收数据
           input [7: 0] s_data,
           output [7: 0] data
       );

//master产生数据，产生valid信号

reg [7: 0] m_data_r;
reg m_valid_r; //master输出valid
reg m_ready_r; //来自slave的ready信号打一拍
reg m_ready_rr;  //打两拍

assign m_data = m_data_r;
assign m_valid = m_valid_r;

always@(posedge m_clk or negedge m_rst_n)
	begin
		if (!m_rst_n)
			begin
				m_data_r <= 8'h00;
				m_valid_r <= 1'b0;
				m_ready_r <= 1'b0;
				m_ready_rr <= 1'b0;
			end
		else
			begin
				{m_ready_rr, m_ready_r} <= {m_ready_r, m_ready};
				m_data_r <= (m_ready_rr == 1'b1) ? 8'h55 : 8'h00;
				m_valid_r <= (m_ready_rr == 1'b1) ? 1'b1 : 1'b0;
			end
	end

//slave接收数据，产生ready信号
reg s_ready_r;
reg s_valid_r;
reg s_valid_rr;

reg [7: 0] data_r;

assign s_ready = s_ready_r;
assign data = data_r;

always@(posedge s_clk or negedge s_rst_n)
	begin
		if (!s_rst_n)
			begin
				s_ready_r <= 1'b0;
				s_valid_r <= 1'b0;
				s_valid_rr <= 1'b0;
				data_r <= 8'h00;
			end
		else
			begin
				{s_valid_rr, s_valid_r} <= {s_valid_r, s_valid};
				s_ready_r <= {s_valid_rr == 1'b0} ? 1'b1 : 1'b0;
				data_r <= (s_valid_rr == 1'b1) ? s_data : 8'H00;
			end
	end
endmodule
